CY62157EV18 MoBL®
8-Mbit (512K x 16) Static RAM
deselected (CE HIGH or CE LOW or both BHE and BLE are
Features
1
2
HIGH). The input and output pins (IO through IO ) are
0
15
• Very high speed: 55 ns
placed in a high impedance state when:
• Deselected (CE HIGH or CE LOW)
• Wide voltage range: 1.65V–2.25V
• Pin Compatible with CY62157DV18 and CY62157DV20
• Ultra low standby power
1
2
• Outputs are disabled (OE HIGH)
• Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH) or
— Typical Standby current: 2 µA
— Maximum Standby current: 8 µA
• Ultra low active power
• Write operation is active (CE LOW, CE HIGH and WE
1
2
LOW).
Write to the device by taking Chip Enables (CE LOW and CE
— Typical active current: 1.8 mA @ f = 1 MHz
• Easy memory expansion with CE , CE and OE features
1
2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from IO pins (IO through IO ), is
1
2
0
7
• Automatic power down when deselected
• CMOS for optimum speed and power
• Available in Pb-free 48-ball VFBGA package
written into the location specified on the address pins (A
0
through A ). If Byte High Enable (BHE) is LOW, then data
18
from IO pins (IO through IO ) is written into the location
8
15
specified on the address pins (A through A ).
0
18
Functional Description [1]
Read from the device by taking Chip Enables (CE LOW and
1
The CY62157EV18 is a high performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra low active current.
CE HIGH) and Output Enable (OE) LOW while forcing the
2
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
®
This is ideal for providing More Battery Life™ (MoBL ) in
pins appear on IO to IO . If Byte High Enable (BHE) is LOW,
0
7
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption when addresses are not toggling.
The device can also be put into standby mode when
8
15
modes.
Product Portfolio
Power Dissipation
Speed
(ns)
Operating I , (mA)
V
Range (V)
Product
CC
CC
Standby, I
(µA)
SB2
f = f
f = 1MHz
max
[2]
[2]
Min
Max
Max
Max
25
Max
Typ
Typ
Typ
Typ
CY62157EV18
1.65
1.8
2.25
55
1.8
3
18
2
8
Notes
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” located at http://www.cypress.com.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V , T = 25°C.
CC
CC(typ)
A
Cypress Semiconductor Corporation
Document #: 38-05490 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 30, 2007
CY62157EV18 MoBL®
Maximum Ratings
DC Input Voltage
......... –0.2V to 2.45V (V
+ 0.2V)
CCmax
Output Current into Outputs (LOW) ............................ 20 mA
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage ......................................... > 2001V
(in accordance with MIL-STD-883, Method 3015)
Storage Temperature ................................–65°C to + 150°C
Ambient Temperature with
Power Applied ...........................................–55°C to + 125°C
Latch-up Current ................................................... > 200 mA
Operating Range
Supply Voltage to Ground
Potential...............................–0.2V to 2.45V (V
+ 0.2V)
+ 0.2V)
CCmax
Ambient
Device
Range
V
CC
Temperature
DC Voltage Applied to Outputs
CY62157EV18LL Industrial –40°C to +85°C 1.65V to 2.25V
in High-Z State
..............–0.2V to 2.45V (V
CCmax
Electrical Characteristics (Over the Operating Range)
55 ns
Parameter
Description
Test Conditions
Unit
Min
Max
Typ
V
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
I
I
= –0.1 mA
= 0.1 mA
V
V
= 1.65V
= 1.65V
1.4
V
V
OH
OL
IH
OH
CC
V
V
V
I
0.2
OL
CC
V
V
= 1.65V to 2.25V
= 1.65V to 2.25V
1.4
–0.2
–1
V
+ 0.2V
CC
V
CC
CC
0.4
+1
V
IL
Input Leakage
Current
GND < V < V
CC
µA
IX
I
I
I
Output Leakage
Current
GND < V < V , Output Disabled
–1
+1
µA
OZ
O
CC
V
Operating Supply
f = f
= 1/t
V
= V
CC(max)
18
25
3
mA
mA
CC
CC
max
RC
CC
Current
I
= 0 mA
OUT
f = 1 MHz
1.8
CMOS levels
I
I
Automatic CEPower Down CE > V −0.2V or CE < 0.2V
2
8
µA
SB1
1
CC
2
Current–CMOS Inputs
V
> V – 0.2V, V < 0.2V)
CC IN
IN
f = f
(Address and Data Only),
max
V
= V
.
f = 0 (OE, WE, BHE and BLE),
CC
CC(max)
[7]
Automatic CE Power Down CE > V – 0.2V or CE < 0.2V,
2
8
µA
1
CC
2
SB2
Current–CMOS Inputs
V
> V – 0.2V or V < 0.2V,
CC IN
IN
f = 0, V = V
.
CC
CC(max)
Capacitance [8]
Parameter
Description
Input Capacitance
Test Conditions
T = 25°C, f = 1 MHz, V = V
CC(typ)
Max
Unit
pF
C
C
10
10
IN
A
CC
Output Capacitance
pF
OUT
Notes
4.
V
= –2.0V for pulse durations less than 20 ns.
IL(min)
5.
V
= V + 0.5V for pulse durations less than 20 ns.
IH(max)
CC
6. Full Device AC operation assumes a 100 µs ramp time from 0 to V (min) and 200 µs wait time after V stabilization.
CC
CC
7. Only chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the I
spec. Other inputs can be left floating.
SB2
8. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05490 Rev. *D
Page 3 of 12
CY62157EV18 MoBL®
Thermal Resistance [8]
Parameter
Description
Test Conditions
BGA
Unit
Θ
Thermal Resistance
(Junction to Ambient)
Still air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
72
°C/W
JA
Θ
Thermal Resistance
(Junction to Case)
8.86
°C/W
JC
AC Test Loads and Waveforms
R1
ALL INPUT PULSES
90%
10%
V
CC
3V
OUTPUT
90%
10%
GND
Rise Time = 1 V/ns
R2
30 pF
Fall Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
OUTPUT
THEVENIN EQUIVALENT
R
TH
V
Parameters
Value
Unit
Ω
R1
R2
13500
10800
6000
0.80
Ω
R
Ω
TH
TH
V
V
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
Conditions
Min
Max Unit
Typ
V
V
for Data Retention
1.0
V
DR
CC
I
Data Retention Current
V
= V , CE > V – 0.2V,
1
3
µA
CCDR
CC
DR
1
CC
CE < 0.2V,V > V – 0.2V or V < 0.2V
2
IN
CC
IN
Chip Deselect to Data Retention Time
Operation Recovery Time
0
ns
ns
t
t
CDR
R
t
RC
Data Retention Waveform [10]
DATA RETENTION MODE
V
V
> 1.0V
V
CC(min)
CC(min)
VCC
DR
t
t
CDR
R
CE1 or
BHE.BLE
or
CE2
Notes
9. Full device operation requires linear V ramp from V to V
> 100 µs or stable at V
> 100 µs.
CC(min)
CC
DR
CC(min)
10. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
Document #: 38-05490 Rev. *D
Page 4 of 12
CY62157EV18 MoBL®
]
Switching Characteristics (Over the Operating Range)
55 ns
Parameter
Read Cycle
Description
Unit
Min
Max
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
55
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address to Data Valid
55
AA
Data Hold from Address Change
CE LOW and CE HIGH to Data Valid
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
55
25
1
2
OE LOW to Data Valid
OE LOW to Low-Z
5
10
0
OE HIGH to High-Z
CE LOW and CE HIGH to Low-Z
18
18
1
2
CE HIGH and CE LOW to High-Z
1
2
CE LOW and CE HIGH to Power Up
1
2
CE HIGH and CE LOW to Power Down
55
55
PD
1
2
BLE/BHE LOW to Data Valid
DBE
LZBE
HZBE
BLE/BHE LOW to Low-Z
10
45
BLE/BHE HIGH to High-Z
18
Write Cycle
t
Write Cycle Time
ns
WC
t
t
t
t
CE LOW and CE HIGH to Write End
35
35
0
ns
ns
ns
ns
SCE
AW
HA
1
2
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
0
SA
t
t
t
t
WE Pulse Width
35
35
25
0
ns
ns
ns
ns
ns
PWE
BW
SD
BLE/BHE LOW to Write End
Data Setup to Write End
Data Hold from Write End
HD
t
t
WE LOW to High-Z
18
HZWE
LZWE
WE HIGH to Low-Z
10
ns
Notes
11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1V/ns or less, timing reference levels of V
/2, input pulse
CC(typ)
levels of 0 to V
OL OH
CC(typ)
12. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. Please see application note AN13842 for further
clarification.
13. At any given temperature and voltage condition, t
given device.
is less than t
, t
is less than t
, t
is less than t
, and t
is less than t
for any
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
LZWE
14. t
, t
, t
, and t
transitions are measured when the output enters a high impedance state.
HZWE
HZOE HZCE HZBE
15. If both byte enables are toggled together, this value is 10 ns.
16. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE and/or BLE = V , and CE = V . All signals must be ACTIVE to initiate a
IL
IL
2
IH
write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that
terminates the write.
Document #: 38-05490 Rev. *D
Page 5 of 12
CY62157EV18 MoBL®
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle 2 (OE Controlled)
ADDRESS
tRC
CE1
CE2
tPD
t
HZCE
tACE
BHE/BLE
OE
tDBE
tHZBE
tLZBE
tHZOE
tDOE
tLZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
VCC
SUPPLY
CURRENT
DATA VALID
tLZCE
ICC
ISB
tPU
50%
50%
Notes:
17. The device is continuously selected. OE, CE = V , BHE and/or BLE = V , and CE = V .
IH
1
IL
IL
2
18. WE is HIGH for read cycle.
19. Address valid before or similar to CE , BHE, BLE transition LOW and CE transition HIGH.
1
2
Document #: 38-05490 Rev. *D
Page 6 of 12
CY62157EV18 MoBL®
Switching Waveforms (continued)
Write Cycle 1 (WE Controlled)
tWC
ADDRESS
CE1
tSCE
CE2
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
tHD
tSD
DATA IO
NOTE 22
VALID DATA
tHZOE
Write Cycle 2 (CE or CE Controlled)
1
2
tWC
ADDRESS
CE1
tSCE
CE2
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tHD
tSD
DATA IO
VALID DATA
tHZOE
Notes:
20. Data IO is high impedance if OE = V
.
IH
21. If CE goes HIGH and CE goes LOW simultaneously with WE = V , the output remains in a high impedance state.
1
2
IH
22. During this period, the IOs are in output state and input signals must not be applied.
Document #: 38-05490 Rev. *D
Page 7 of 12
CY62157EV18 MoBL®
Switching Waveforms (continued)
Write Cycle 3 (WE Controlled, OE LOW)
tWC
ADDRESS
CE1
tSCE
CE2
tBW
BHE/BLE
tAW
tHA
tSA
tPWE
WE
tSD
tHD
DATA IO
VALID DATA
tLZWE
t
HZWE
Write Cycle 4 (BHE/BLE Controlled, OE LOW)
tWC
ADDRESS
CE1
CE2
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tSD
tHD
NOTE 22
DATA IO
VALID DATA
Document #: 38-05490 Rev. *D
Page 8 of 12
CY62157EV18 MoBL®
Truth Table
CE
CE
WE
OE
BHE
BLE
Inputs/Outputs
High-Z
Mode
Power
1
2
H
X
X
X
X
X
Deselect/Power Down
Standby (I
)
)
)
SB
SB
SB
X
X
L
L
L
X
H
H
X
X
H
H
X
X
L
L
X
H
L
X
H
L
High-Z
High-Z
Deselect/Power Down
Deselect/Power Down
Read
Standby (I
Standby (I
Data Out (IO –IO
)
Active (I
Active (I
)
)
0
15
CC
CC
H
L
Data Out (IO –IO );
Read
0
7
High-Z (IO –IO
)
8
15
L
H
H
L
L
H
High-Z (IO –IO );
Read
Active (I
)
0
7
CC
Data Out (IO –IO
)
8
15
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
X
X
L
H
L
H
L
L
L
L
High-Z
High-Z
High-Z
Output Disabled
Output Disabled
Output Disabled
Write
Active (I
Active (I
Active (I
Active (I
Active (I
)
)
)
)
)
CC
CC
CC
CC
CC
L
Data In (IO –IO
)
0
15
L
H
Data In (IO –IO );
Write
0
7
High-Z (IO –IO
)
8
15
L
H
L
X
L
H
High-Z (IO –IO );
Write
Active (I
)
0
7
CC
Data In (IO –IO
)
8
15
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Package Type
Ordering Code
55
CY62157EV18LL-55BVXI 51-85150 48-ball Very Fine Pitch Ball Grid Array (Pb-free)
Industrial
Contact your local Cypress sales representative for availability of these parts
Document #: 38-05490 Rev. *D
Page 9 of 12
CY62157EV18 MoBL®
Package Diagrams
Figure 1. 48-ball VFBGA (6 x 8 x 1 mm), 51-85150
BOTTOM VIEW
A1 CORNER
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
Ø0.30 0.05(48X)
A1 CORNER
1
2
3
4
5
6
6
5
4
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.875
A
A
0.75
B
6.00 0.10
3.75
B
6.00 0.10
0.15(4X)
SEATING PLANE
C
51-85150-*D
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names
mentioned in this document are the trademarks of their respective holders.
Document #: 38-05490 Rev. *D
Page 10 of 12
© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to
be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY62157EV18 MoBL®
Document History
®
Document Title: CY62157EV18 MoBL 8-Mbit (512K x 16) Static RAM
Document Number:38-05490
Orig. of
Change
REV. ECN NO. Issue Date
Description of Change
**
202862 See ECN
291272 See ECN
AJU New Data Sheet
*A
SYT Converted from Advance Information to Preliminary
Changed V Max from 2.20 to 2.25 V
CC
Changed V stabilization time in footnote #7 from 100 µs to 200 µs
CC
Changed I
Changed t
Changed t
from 4 to 4.5 µA
from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bins
CCDR
OHA
DOE
from 15 and 22 ns to 18 and 22 ns for the 35 and 45 ns Speed Bins
respectively
Changed t
, t
and t
from 12 and 15 ns to 15 and 18 ns for the 35 and 45
HZOE HZBE
HZWE
ns Speed Bins respectively
Changed t from 12 and 15 ns to 18 and 22 ns for the 35 and 45 ns Speed Bins
HZCE
respectively
Changed t
, t
and t
from 25 and 40 ns to 30 and 35 ns for the 35 and 45 ns
SCE AW,
BW
Speed Bins respectively
Changed t from 15 and 20 ns to 18 and 22 ns for the 35 and 45 ns Speed Bins
SD
respectively
Added Pb-Free Package Information
*B
444306 See ECN
NXR Converted from Preliminary to Final
Removed 35 ns speed bin
Removed “L” bin
Changed ball E3 from DNU to NC
Removed redundant footnote on DNU
Modified Maximum Ratings spec for Supply Voltage and DC Input Voltage from 2.4V to
2.45V
Changed the I Typ value from 16 mA to 18 mA and I Max value from 28 mA to 25
CC
CC
mA for test condition f = fax = 1/t
RC
Changed the I Max value from 2.3 mA to 3 mA for test condition f = 1MHz
CC
Changed the I
and I
Max value from 4.5 µA to 8 µA and Typ value from 0.9 µA
SB2
SB1
to 2 µA respectively
Updated Thermal Resistance table
Changed Test Load Capacitance from 50 pF to 30 pF
Added Typ value for I
CCDR
Changed the I
Max value from 4.5 µA to 3 µA
CCDR
Corrected t in Data Retention Characteristics from 100 µs to t ns
R
RC
Changed t
Changed t
Changed t
Changed t
Changed t
from 3 to 5
from 6 to 10
from 22 to 18
from 6 to 5
LZOE
LZCE
HZCE
LZBE
PWE
from 30 to 35
Changed t from 22 to 25
SD
Changed t
from 6 to 10
LZWE
Added footnote #13
Updated the ordering Information and replaced the Package Name column with
Package Diagram
*C
571786 See ECN
VKN Replaced 45ns speed bin with 55ns
Document #: 38-05490 Rev. *D
Page 11 of 12
CY62157EV18 MoBL®
®
Document Title: CY62157EV18 MoBL 8-Mbit (512K x 16) Static RAM
Document Number:38-05490
Orig. of
Change
REV. ECN NO. Issue Date
Description of Change
*D
908120 See ECN
VKN Added footnote #7 related to I
SB2
Added footnote #12 related AC timing parameters
Document #: 38-05490 Rev. *D
Page 12 of 12
|